1. Field of the Invention
The present invention relates to a method for generating differential tri-states and a differential tri-state circuit being able to output three states including a first signal state, a second signal state and a high impedance state.
2. Description of the Related Art
To transmit a logic signal between integrated circuits by using two signals each having a small-amplitude to be transmitted through transmission paths such as two bus lines in communication systems, computers and the like, two methods, one being a single-phase transmission system and the other being a differential-phase transmission system, are available. In the single-phase transmission system, one small-amplitude signal for transmission use is transmitted through two bus lines. In the differential-phase transmission system, two signals are used, i.e., a small-amplitude signal, which is equivalent to the signal used in the single-phase transmission system, is transmitted through one line of the two bus lines and a small-amplitude signal being in reverse phase is simultaneously transmitted through the other line of the two bus lines.
Operations of the differential-phase transmission system are described below. In the differential-phase transmission system, to transmit a logic signal between integrated circuits by using two signals to be transmitted through two bus lines, an output circuit to send out a logic signal to these transmission paths is used. If one signal being transmitted through one of two transmission paths is at a high level, it is defined as a logical 1 and the other signal being transmitted through the other of the two transmission paths is at a low level, it is defined as a logical 0 (zero). That is, a logic signal (hereinafter referred to as a "transmission signal") to be transmitted by the output circuit is composed of two signals to be transmitted through the two transmission paths. Moreover, when the output circuit is outputting the logical 1 or 0, it is hereinafter defined that "the output circuit is outputting the 1 state or 0 state".
Conventionally, an amplitude of a voltage between a high level signal and a low level signal is near to that of a supply power voltage applied to integrated circuits in most cases. However, in recent years, the amplitude of the voltage applied between the high level signal and the low level signal is made small for transmission purpose. For example, in an output circuit using conventional CMOS interface specifications, an amplitude of the transmission signal is approximately equal to a supply power voltage, i.e., about 5 volts or about 3 volts, in general. On the other hand, in an output circuit using LVDS (Low Voltage Differential Signaling) interface specifications, an amplitude of the transmission signal is as extremely small as about 0.3 volts.
The reasons for making an amplitude of the transmission signal so small are that such a small-amplitude signal is greatly effective in high speed transmission, low power consumption and reduction of noise occurring during the signal transmission. Therefore, in an integrated circuit seeking high speed transmission and low power consumption, it is necessary to use a small-amplitude interfacing output circuit to send out a signal having a small-amplitude. In such a small-amplitude interfacing output circuit, a transmission signal having a small-amplitude voltage being less than the power supply voltage is employed to achieve the high speed transmission, low power consumption and reduction of noise. Known small-amplitude interfacing output circuits include, in addition to the LVDS circuit described above, GRL (Gunng Transceiver Logic), CTT (Center Tapped Termination), PECL (Psuedo Emirter Coupled Logic) circuits.
For example, in the case of the PECL circuit, though its power supply voltage is about 3 volts or 5 volts, an amplitude of a transmission signal to be employed is about 0.6 volts. As a means to transfer such small-amplitude signals, a terminating voltage source and terminating resistors are used.
A conventional small-amplitude interfacing output circuit having the configurations described above is shown in FIG. 12. The small-amplitude interfacing output circuit contains a differential tri-state circuit 1T. Though the terminating voltage source VS and terminating resistors RT1 and Rt2 to be used in the small-amplitude interfacing output circuit are connected to transfer lines L1 and L2 as shown in FIG. 12, they may be mounted within the differential tri-state circuit as shown in FIG. 9. However, even if the terminating voltage source VS is mounted within the differential tri-state circuit, the terminating voltage is supplied through the transfer lines L1 and L2 to the outside.
The differential tri-state circuit 1T is connected to, for example, a CMOS internal circuit 52 of a first integrated circuit 50. The transfer lines L1 and L2 are connected to an input circuit 1R of a second integrated circuit 54 to receive a transmission signal. The input circuit 1R is connected to a CMOS internal circuit 56.
As shown in FIGS. 9 and 10, the differential tri-state circuit 1T is comprised of a current source 2, a current source 4, a switching circuit 1S in which a drain of a p-channel MOS FET P3 is connected to a drain of an n-channel MOS FET N3, a source of the p-channel MOS FET P3 is connected to a flow-out terminal NodeP of the current source 2, a source of an n-channel MOS FET N3 is connected to an inflow terminal NodeN of the current source 4, a drain of a p-channel MOS FET P4 is connected to a drain of an n-channel MOS FET N4, a source of the p-channel MOS FET P4 is connected to the flow-out NodeP of the current source 2 and a source of an n-channel MOS FET N4 is connected to the inflow terminal NodeN of the current source 4 and a switching voltage generating circuit 10 in which an output terminal 21 used to output a switching voltage signal APA is connected to a gate of the p-channel MOS FET P3, an output terminal 29 used to output a switching voltage signal APB is connected to a gate of the p-channel MOS FET P4, an output terminal 25 to output a switching voltage signal ANA is connected to a gate of the n-channel MOS FET N3 and an output terminal 31 to output a switching voltage signal ANB is connected to a gate of the n-channel MOS FET N4.
The p-channel MOS FETs P3 and P4 are composed of MOS FETs which have been produced under the same manufacturing conditions and have the same configurations. The n-channel MOS FETs N3 and N4 are composed of MOS FETs which have been produced under the same manufacturing conditions and have the same configurations.
The current source 2 is comprised of a p-channel MOS FET P1 a source of which is connected to a voltage source VDD having, for example, a predetermined voltage being 3 volts and a drain of which is connected to a current flow-out terminal NodeP, a p-channel MOS FET P2 a source of which is connected to the voltage source VDD, a gate of which is connected to a gate of the p-channel MOS FET P1 and the gate and a drain of which are connected to each other, and a current source 6 connected between the drain of the p-channel MOS FET P2 and a ground potential point.
The current source 4 is comprised of an n-channel MOS FET N1 a source of which is connected to a predetermined voltage value point, for example, a ground potential point and a drain of which is connected to a current flow-out terminal NodeN1, an n-channel MOS FET N2 a source of which is connected to a ground potential point, a gate of which is connected to a gate of the n-channel MOS FET N1 and the gate and a drain of which are connected to each other and a current source 8 connected between a drain of the n-channel MOS FET N2 and a voltage source VDD.
A switching voltage supply circuit 10 has a switching voltage generating portion 10S which is comprised of inverters 16 and 18 connected in series to an input terminal 12, a NAND circuit 20 one input of which is connected to an output of the inverter 18 and the other input of which is connected to an enable terminal 14, an inverter 22 an input of which is connected to the enable terminal 14, a NOR circuit one input of which is connected to the output of the inverter 18 and the other input of which is connected to an output of the inverter 22, a buffer 26 an input of which is connected to an output of the inverter 16, a NAND circuit 28 one input of which is connected to an output of the buffer and the other input of which is connected to the enable terminal 14 and a NOR circuit 30 one input of which is connected to an output of the buffer 26 and the other input of which is connected to an output of the inverter 22.
The switching voltage generating circuit 10 is so configured that a switching voltage signal APA is outputted from an output terminal 21 of the NAND circuit 20, a switching voltage signal ANA is outputted from an output terminal 25 of the NOR circuit 24, a switching voltage signal APB is outputted from an output terminal 29 of the NAND circuit 28 and a switching voltage signal ANB is outputted from an output terminal 31 of the NOR circuit 30.
A connection point between the drain of the p-channel MOS FET P3 and the drain of the n-channel MOS FET N3 is one output terminal OUTA of the differential tri-state circuit 1T and a connection point between the drain of the p-channel MOS FET P4 and the drain of the n-channel MOS FET N4 is the other output terminal OUTB of the same. For example, in a small-amplitude interfacing output circuit using the PECL specifications, the small-amplitude interfacing output circuit 1T as shown in FIG. 9 is employed in which terminating resistors RT1 and RT2 are connected in series between the output terminals OUTA and OUTB and a terminating supply voltage source VS is connected to a connection point between the terminating resistors RT1 and RT2.
Operations of the conventional differential tri-state circuit having the configurations described above are described below by referring to FIGS. 9, 10 and 11.
In a state where a low-level input signal IN is fed to an input terminal 12 of the switching voltage generating circuit 10 and the enable signal EN is fed to the enable terminal 14 (see the signal EN in FIG. 11), the switching voltage signals APA and APB are at a voltage level to put the differential tri-state circuit 1T in its disabled state, i.e., at a high level, while the switching voltage signals ANA and ANB are at a voltage to put the differential tri-state circuit 1T in its disabled state, i.e., at a low level.
When the high-level switching voltage signal APA is fed to the gate of the p-channel MOS FET P3, the high-level switching voltage APB is fed to the gate of the p-channel MOS FET P4, the low-level switching signal ANA is fed to the gate of the n-channel MOS FET N3 and the low-level switching voltage signal ANB is fed to the gate of the n-channel MOS FET N4, all these transistors are brought out of conduction, i.e., they are all turned OFF and no currents flow through any path from the current source 2 toward the current source 4, causing one output terminal OUTA and the other output terminal OUTB of the differential tri-state circuit to be at a voltage VTT of the terminating supply voltage source VS and to be put in a high impedance state (see a period 1 of the signals OUTA and OUTB in FIG. 11). A voltage of the NodeP becomes VDD and the voltage of the NodeN is at a ground potential.
While the input signal IN remains at a low level (during the period i 2 of the signal IN in FIG. 11), if the differential tri-state circuit is switched from its disabled state to its enabled state, for example, if a high-level enable signal EN is inputted, a level of the switching voltage signal APB generated from the switching voltage generating circuit 10 becomes low and a level of the switching voltage signal ANA becomes high. At this point, the switching voltage signal APA remains at a high level and the switching voltage signal ANB remains at a low level. Since the high-level switching voltage signal APA and the low-level switching voltage signal ANB are fed respectively to each of the gates of the p-channel MOS FET P3 and the n-channel MOS FET N4, these transistors remain OFF, while, since the switching voltage signal APB a level of which has become low is fed to the gate of the p-channel MOS FET and the switching voltage signal ANA a level of which has become high is fed to the gate of the n-channel MOS FET, these transistors P4 and N3 are turned ON. Accordingly, the current I flows from the current source 2 through the p-channel MOS FET which has been,turned ON, terminating resistors RT2 and RT1 and n-channel MOS FET N3 to the current source 4. That is, a signal which is at a high level at the output terminal OUTB and at a low at the OUTA is generated between the terminating resistors RT2 and RT1. Either of these two voltage levels is defined as a 1 state or 0 state. By making low a level of the switching voltage signal APA of the switching voltage generating circuit 10, making high a level of the switching voltage signal ANB, and by causing the switching voltage signal APB to remain at a high level and the switching voltage signal ANA to remain at a low level, the current I flows from the current source 2 through the p-channel MOS FET P3 which has been turned ON, terminating resistors RT2 and RT1 and the n-channel MOS FET N4 to the current source 4. That is, a signal which is at a high level at the output terminal OUTA and at a low at the OUTB is generated between the terminating resistors RT2 and RT1. Either of these two voltage levels is defined as a 1 state or 0 state.
However, during the period 2 of the signal output in FIG. 11, since the current I flows after a transition of the enable signal EN to a high level, a transition of a voltage at the NodeP to lower voltage by .DELTA. volt, for example, by one volt, takes place as shown in the signal NodeP in FIG. 11. The voltage transition causes a transient drop in the gate voltage VGP of the transistor P1 due to the addition of parasitic capacity CP between the drain and gate of the p-channel MOS FET P1 (see the signal VGP in FIG. 11). At the same time, a transition of a voltage at the flow-out terminal NodeN by .DELTA. volt, for example, by one volt, takes place as shown in the signal NodeN in FIG. 11. The voltage transition causes a transient rise in the gate voltage VGN of the transistor P1 due to the addition of parasitic capacity CN between the drain and gate of the n-channel MOS FET N1 (see the signal VGN in FIG. 11).
The great transient flow of the current I causes a swing in voltages occurring at the output terminal OUTB toward a positive direction (see the signal OUTB in FIG. 11) as well as a swing in voltages occurring simultaneously at the output terminal OUTA toward a negative direction (see the signal OUTA in FIG. 11). As a result, a transient increase is produced in an amplitude of the output signal occurring between the output terminals OUTA and OUTB, which causes not only a departure from amplitude specifications but transient noise and malfunctions.